Description

168 Pin Registered Dual In-Line Memory Modules described within this document utilize 64Mb Synchronous DRAM technology. This document should be used in conjunction with the individual DIMM application specifications that contain specific data (to each DIMM) such as the AC characteristics, block diagrams, etc. The information presented here allows one to better understand and analyze both the basic cycle operation, as well as the timings, involved in a registered SDRAM DIMM.

All 168 Pin Registered DIMMs conform to a compatible set of timing and operation characteristics intended to comply with the 100 MHz registered standards.

The Registered DIMMs achieve high speed data transfer rates of up to 100MHz by employing a prefetch/pipeline hybrid architecture that supports the JEDEC 1N rule, while allowing low burst power.

All control and address signals are synchronized with the positive edge of externally supplied clocks and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM devices. This pipelining allows the path between the memory controller and the DIMMs to be achieved in two clock cycles rather than one. Use of an on-board register also reduces the capacitive loading of the DIMM on input control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM tabs through 10 Ohm series resistors. All timing diagrams and explanations show DIMM operation at the tabs, not SDRAM operation.

This document provides a sample of the operations supported by the 168 Pin Registered SDRAM module when used in Registered Mode, both in CAS latency and burst length (see the 168 Pin Synchronous Unbuffered/Buffered Functional Description Specification when using these DIMMs in buffered Mode).

The picture below depicts an overview of the effect of the Registered Mode on the data outputs (DQs) for a Read operation. Without the register, the data is delayed according to the device CAS latency, in this case three clocks. With the register, the data is delayed according to the device CAS latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example is four clocks. The data path can be thought of as a pipeline in which the register effectively lengthens the pipe by one clock cycle. All diagrams within this document refer to the DIMM CAS latency and take into account the register.



Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs.

Like a conventional DRAM, the Synchronous DRAMs on the DIMM must be powered up and initialized in a predefined manner. During power on, all VDD pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK0 signal must be started at the same time. After power on, an initial pause of 200Ás is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQMB and CKE0 pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. In addition, no DIMM operation can be performed for at least 1 ms to allow on-board PLL, if present, to stabilize and lock onto the system clock inputs.



Programming the Mode Register
For application flexibility, device CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set command. Contents of the Mode Register are altered by re-executing the Mode Register Set command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set command is issued.

After initial power up, the Mode Register Set command must be issued before Read or Write cycles may begin. All four device banks must be in a precharged state and CKE0 must be high at least one cycle before the Mode Register Set command can be issued. The Mode Register Set command is activated by the low signals of RAS, CAS, SN and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the Mode Register Set command once a delay equal to tRSC has elapsed.



DIMM CAS Latency
DIMM CAS latency is a parameter that defines the delay from when a Read command is registered on a rising clock edge to when the data from that Read command becomes available at the outputs. DIMM CAS latency is expressed in clock cycles.

Do not confuse DIMM CAS latency with the SDRAM CAS latency, which is one clock less. Once the appropriate SDRAM device CAS latency has been selected, it must be programmed into the mode register after power up. For an explanation of this procedure see the previous section, Programming the Mode Register.



Burst Mode Operation
Burst mode operation provides a constant data flow to memory locations (Write cycle), or from memory locations (Read cycle). Three parameters define how the burst mode will operate: burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are defined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A8 - A13.

The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the Burst Length and Sequence Table below.

The burst length controls the number of bits that will be output after a Read command, or the number of bits to be input after a Write command. The burst length can be programmed to values of 1, 2, 4, 8 or full page (actual page length is dependent on SDRAM device organization: x4 or x8). Full page Burst operation is only possible using the sequential burst type.

Burst operation mode can be normal operation or multiple burst with single Write operation. Normal operation implies that the device will perform Burst operations on both Read and Write cycles until the desired burst length is satisfied. Multiple burst with single Write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to Read cycles. All Write cycles are single Write operations when this mode is selected.



Burst Length and Sequence

Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal)
2 x x 0 0, 1 0, 1
x x 1 1, 0 1, 0
4 x 0 0 0, 1, 2, 3 0, 1, 2, 3
x 0 1 1, 2, 3, 0 1, 0, 3, 2
x 1 0 2, 3, 0, 1 2, 3, 0, 1
x 1 1 3, 0, 1, 2 3, 2, 1, 0
8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
Full Page (Note) n n n Cn, Cn+1, Cn+2, ...... Not Supported

Note: Page length is a function of I/O organization and column addressing.

Device x4 organization (CA0-CA9); Page Length = 1024 bits

Device x8 organization (CA0-CA8); Page Length = 512 bits



Bank Activate Command
In order to activate a logical bank in the SDRAM, the Bank Activate command must be issued. The Bank Activate command is invoked by holding CAS and WE high with SN on one deck and RAS low at the rising edge of the clock. The bank select address BA0 - BA1 is used to select the desired bank (as shown in the Bank Select section below). The row address A0 - A11 is used to determine which row to activate in the selected bank. Activation of banks within both decks of a 2-High stacked device is allowed.

The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first Read or Write operation can begin must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another row can be accessed from the same logical bank. After precharge the Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (for example Bank A to Bank B) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max).



Bank Select
The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation.




Bank Selection Bits

BA0 BA1 Bank
0 0 Bank A
0 1 Bank B
1 0 Bank C
1 1 Bank D



Read and Write Access Modes
After a bank has been activated, a Read or Write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock's rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine whether the Access cycle is a Read operation (WE high), or a Write operation (WE low). The address inputs determine the starting column address.

The SDRAM DIMM provides a wide variety of fast access modes. A single Read or Write command will initiate a serial Read or Write operation on successive clock cycles at data rates of up to 100MHz. The number of serial data bits for each access is equal to the burst length, programmed into the Mode Register. Although the burst length is user programmable, the boundary of the Burst cycle is restricted to specific segments of the page length. If the burst length is full page, data is repeatedly read out or written until a Burst Stop or Precharge command is issued.

Similar to Page Mode of conventional DRAMs, a Read or Write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1N rule. When the previous burst is interrupted by another Read or Write command, the remaining addresses are overridden by the new address.

Precharging an active bank after each Read or Write operation is not necessary providing the same row is to be accessed again. To perform a Read or Write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the Access and Precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, Column to Column interleave operation can be done between different pages. Finally, Read or Write commands can be issued to the same bank or between active banks on every clock cycle.



Burst Read Command
The Burst Read command is initiated by having SN on one deck and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the device CAS latency that is set in the Mode Register plus one clock cycle due to the on-DIMM pipeline register.



Read Interrupted by a Read Command
A Burst Read may be interrupted before completion of the burst by another Read command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the DIMM CAS latency from the interrupting Read command is satisfied, at this point the data from the interrupting Read command appears.



Burst Write Command
The Burst Write command is initiated by having SN on one deck, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no DIMM CAS latency required for Burst Write cycles, but the data is delayed one clock cycle due to the on-DIMM pipeline register. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the next clock cycle after the Write command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.




Read Interrupted by a Write Command
To interrupt a burst read with a Write command, DQMB may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read command will issue data on the first and second clocks' cycles of the write operation, DQMB is needed to insure the DQs are tri-stated. After that point the Write command has control of the DQ bus.



Write Interrupted by a Write
A Burst write may be interrupted before completion of the burst by another Write command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.


Write Interrupted by a Read Command
A Read command will interrupt a Burst Write operation on the next clock cycle after the Read command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read command is registered, any residual data from the Burst Write cycle will be ignored. Data that is presented on the DQ tabs before and during the cycle that the Read command is initiated will actually be written to the memory.



Burst Stop Command
Once a Burst Read or Write operation has been initiated, there exist several methods with which to terminate the Burst operation prematurely. These methods include using another Read or Write command to interrupt an existing Burst operation or using a Precharge command to interrupt a Burst cycle and close the active bank. When interrupting a burst with another Read or Write command, care must be taken to avoid DQ contention.

If the burst length is full page, the Burst Stop command may also be used to terminate the existing burst operation, but leave the bank open for future Read or Write commands to the same page of the active bank. Use of the Burst Stop command during other burst length operations is illegal. The Burst Stop command is defined by having RAS and CAS high with SN on one deck and WE low at the rising edge of the clock.

When using the Burst Stop command during a Burst Read cycle, the data DQs go to a high impedance state after a delay which is equal to the DIMM CAS latency.

If a Burst Stop command is issued during a full page Burst Write operation, then any residual data from the Burst Write cycle will be ignored. Data that is presented on the DQ tabs up to and including the cycle when the Burst Stop command is registered will be written to the memory.


Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the auto-precharge function. When a Read or a Write command is given to the DIMM, the CAS timing accepts one extra address, column address A10/AP, to allow the active bank to automatically begin precharge at the earliest possible moment during the Burst Read or Write cycle. If A10/AP is low when the READ or WRITE command is issued, then normal Read or Write Burst operation is executed and the bank remains active at the completion of the burst sequence. If A10/AP is high when the Read or Write command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read command will execute as normal with the exception that the active bank will begin to precharge before all Burst Read cycles have been completed. It will begin to precharge after a delay equal to the burst length plus one clock cycle, expressed in clocks. This feature allows the precharge operation to be partially or completely hidden during the Burst Read cycles (dependent upon DIMM CAS latency) thus improving system performance for random data access. Auto-precharge can also be implemented during Write commands, although precharge can not begin any sooner than is possible by issuing the Precharge command directly to the device.

A Read or Write command without auto-precharge can be terminated in the midst of a Burst operation. However, a Read or Write command with auto-precharge can not be interrupted before the entire Burst operation is completed. Therefore use of a Read, Write, or Precharge command is prohibited during a Read or Write cycle with auto-precharge. Once the Precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. It should be noted that the device will not respond to the Auto-Precharge command if the device is programmed for full page burst Read or Write cycles, or full page Burst Read cycles with single Write operation.


Burst Write with Auto-Precharge
If A10/AP is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the Precharge operation one clock delay from the last Burst Write cycle. This delay is referred to as tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP).



Burst Write with Auto-Precharge (Burst Length = 4, DIMM CAS Latency = 3,4)

When using the Auto-Precharge command, the interval between the Bank Activate command and the beginning of the internal Precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended.


Precharge Command
The Precharge command is used to precharge or close a bank that has been activated. The Precharge command is triggered when SN on one deck, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10/AP, BA0, and BA1, define which bank(s) are precharged when the command is issued.


Bank Selection for Precharge by Address Bits

A10/AP Bank Select Precharged Bank(s)
LOW BA0, BA1 Bank defined by BA0, BA1 only
HIGH DON'T CARE All Banks


After the Precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge command and the Activate command must be greater than or equal to the Precharge time (tRP).

For Read cycles, the Precharge command may be applied consistent with the third to last burst of Read data (or later). The DQs go to a high impedance state after a delay equal to the DIMM CAS latency.

For Write cycles, however, a delay must be satisfied from the start of the last Burst Write cycle until the Precharge command can be issued. This delay is known as tDPL, Data-in to Precharge Delay.


Precharge Termination

The Precharge command terminates either a Burst Read or Burst Write operation. When the Precharge command is issued, the Burst operation is terminated and bank precharge begins. For Burst Read operations, valid data will continue to appear on the data bus as a function of DIMM CAS Latency.

Burst Write operations are terminated by the Precharge command. The last write data properly stored is that write data that is presented to the device on the same clock as the Precharge command.


Automatic Refresh Command (CAS Before RAS Refresh, CBR)
When SN on one deck, RAS and CAS are held low with CKE0 and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. For a stacked device, both decks may be refreshed at the same time using Automatic Refresh Mode. An address counter, internal to the device, provides the address during the Refresh cycle. No control of the external address pins is required once this cycle has started.

When the Refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh command (CBR) and the next Activate command or subsequent Auto Refresh command must be greater than or equal to the RAS cycle time (tRC).


Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh command is defined by having SN, RAS, CAS and CKE0 held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh command. Once the command is registered, CKE0 must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE0, are disabled. The clock is internally disabled during Self Refresh operation to save power. The user may halt the external clock while the device is in Self Refresh mode. However, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE0 is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). When using Self Refresh, both decks of a stacked device may be refreshed at the same time.


Power Down Mode
In order to reduce standby power consumption, a power down mode is available.Once the Power Down mode is initiated by holding CKE0 low, all of the receiver circuits except CK0 and CKE0 are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device.

The Power Down mode is exited by bringing CKE0 high. When CKE0 goes high, a No Operation command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE0 held high for a period equal to tCES(min) + tCK(min). (See Power Down Mode Exit Timing below.)




Power Down Mode Exit Timing


Data Mask
The SDRAM DIMM has a Data Mask function that can be used in conjunction with data Read and Write cycles. When the Data Mask is activated (DQMB high) during a Write cycle, the Write operation is prohibited on the next clock cycle. If the Data Mask is activated during a Read cycle, the data outputs are disabled and become high impedance after a three clock delay, independent of CAS latency.



No Operation (NOP) Command
The NOP command should be used in cases when the SDRAMs are in an idle or a wait state. The purpose of the NOP command is to prevent the SDRAMs from registering any unwanted commands between operations. A No Operation command is registered when SN on one deck is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation command will not terminate a previous operation that is still executing, such as a Burst Read or Write cycle.


Deselect Command
The Deselect command performs the same function as a No Operation command. Deselect command occurs when SN on one deck is brought high, the RAS, CAS, and WE signals then become don't cares.


Clock Suspend Mode
During normal access mode, CKE0 is held high enabling the clock. When CKE0 is registered low while at least one of the banks is active, Clock Suspend mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. There is a two clock delay between the registration of CKE0 low and the time at which the SDRAMs' operation suspends. While in Clock Suspend mode, the SDRAMs ignore any new commands that are issued. The Clock Suspend mode is exited by bringing CKE0 high. There is a two clock cycle delay from when CKE0 returns high to when Clock Suspend mode is exited.

When SDRAM operation is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.

If Clock Suspend mode is initiated during a burst write operation, then the input data is masked and ignored until the Clock Suspend mode is exited.

 

Truth Table


Command Truth Table

Function Device

State

CKE0 SN RAS CAS WE DQMB BA0,

BA1

A10 A11,

A9-A0

Notes
Previous Cycle Current Cycle
Mode Register Set Idle H X L L L L X OP Code  
Auto (CBR) Refresh Idle H H L L L H X X X X  
Entry Self Refresh Idle H L L L L H X X X X  
Exit Self Refresh Idle

(Self-Refresh)

L H H X X X X X X X  
L H H X
Single Bank Precharge See Current State Table H X L L H L X BS L X 1
Precharge all Banks See Current State Table H X L L H L X X H X  
Bank Activate Idle H X L L H H X BS Row Address 1
Write Active H X L H L L X BS L Column 1
Write with Auto-Precharge Active H X L H L L X BS H Column 1
Read Active H X L H L H X BS L Column 1
Read with Auto-Precharge Active H X L H L H X BS H Column 1
Burst Termination Active H X L H H L X X X X 2, 7
No Operation Any H X L H H H X X X X  
Device Deselect Any H X H X X X X X X X  
Clock Suspend Mode Entry Active H L X X X X X X X X 3
Clock Suspend Mode Exit Active L H X X X X X X X X
Data Write/Output Enable Active H X X X X X L X X X 4
Data Mask/Output Disable Active H X X X X X H X X X
Power Down Mode Entry Idle/Active H L H X X X X X X X 5, 6
L H H X
Power Down Mode Exit Any

(Power Down)

L H H X X X X X X X 5, 6
L H H X
  1. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank A; BA0, BA1 = 0,1 selects bank B; BA0, BA1 = 1,0 selects bank C; BA0, BA1 = 1,1 selects bank D.
  2. During a Burst Write cycle there is a one clock delay due to the on-DIMM pipeline register. For a Burst Read cycle the delay is equal to the DIMM CAS latency.
  3. During normal access mode, CKE0 is held high and CK0 is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. A two clock delay is required for mode entry and exit.
  4. The DQMB has two functions for the data DQ Read and Write operations. During a Read cycle, when DQMB goes high at a clock timing the data outputs are disabled and become high impedance after a three clock delay. DQMB also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (on the next clock cycle).
  5. All banks must be precharged before entering the Power Down Mode.(If this command is issued during a burst operation, the device state will be clock suspend mode.)The Power Down Mode does not perform any refresh operations, therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
  6. If SN is low, then when CKE0 returns high, no command is registered into the chip for two clock cycles.
  7. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.



Clock Enable (CKE0) Truth Table

Current State CKE0 Command Action Notes
Previous Cycle Current Cycle SN RAS CAS WE A12, A13 A11 - A0
Self Refresh H X X X X X X X INVALID 1
L H H X X X X X Exit Self Refresh with Device Deselect 2
L H L H H H X X Exit Self Refresh with No Operation 2
L H L H H L X X ILLEGAL 2
L H L H L X X X ILLEGAL 2
L H L L X X X X ILLEGAL 2
L L X X X X X X Maintain Self Refresh  
Power Down H X X X X X X X INVALID 1
L H H X X X X X Power Down mode exit, all banks idle 2
L H L X X X X X ILLEGAL 2
L L X X X X X X Maintain Power Down Mode  
All Banks Idle H H H X X X     Refer to the Idle State section of the Current State Truth Table 3
H H L H X X     3
H H L L H X     3
H H L L L H X X CBR Refresh  
H H L L L L OP Code Mode Register Set 4
H L H X X X     Refer to the Idle State section of the Current State Truth Table 3
H L L H X X     3
H L L L H X     3
H L L L L H X X Entry Self Refresh 4
H L L L L L OP Code Mode Register Set  
L X X X X X X X Power Down 4
Any State other than listed above H H X X X X X X Refer to operations in the Current State Truth Table  
H L X X X X X X Begin Clock Suspend next cycle 5
L H X X X X X X Exit Clock Suspend next cycle  
L L X X X X X X Maintain Clock Suspend  
  1. For the given Current State, CKE0 must be low in the previous cycle.
  2. When CKE0 has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE0 (tCES) must be satisfied before any command other than Exit is issued. When exiting power down mode, a NOP command may be required on the first rising clock after CKE goes high.
  3. The address inputs (A13 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.
  4. The Power Down Mode and the Mode Register Set can only be entered from the all banks idle state.
  5. Must be a legal command as defined in the Current State Truth Table.



Current State Truth Table

Current State Command Action Notes
SN RAS CAS WE A12, A13 A11 - A0 Description
Idle L L L L OP Code Mode Register Set Set the Mode Register 1
L L L H X X Auto or Self Refresh Start Auto or Self Refresh 1, 2
L L H L BS X Precharge No Operation  
L L H H BS Row Address Bank Activate Activate the specified bank and row  
L H L L BS Column Write w/o Precharge ILLEGAL 3
L H L H BS Column Read w/o Precharge ILLEGAL 3
L H H L X X Burst Termination No Operation  
L H H H X X No Operation No Operation  
H X X X X X Device Deselect No Operation or Power Down 4
Row Active L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge Precharge 5
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write Start Write; Determine if Auto Precharge 6, 7
L H L H BS Column Read Start Read; Determine if Auto Precharge 6, 7
L H H L X X Burst Termination No Operation  
L H H H X X No Operation No Operation  
H X X X X X Device Deselect No Operation  
Read L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge Terminate Burst; Start the Precharge  
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write Terminate Burst; Start the Write cycle 7, 8
L H L H BS Column Read Terminate Burst; Start a new Read cycle 7, 8
L H H L X X Burst Termination Terminate the Burst  
L H H H X X No Operation Continue the Burst  
H X X X X X Device Deselect Continue the Burst  
Write L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge Terminate Burst; Start the Precharge  
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write Terminate Burst; Start a new Write cycle 7, 8
L H L H BS Column Read Terminate Burst; Start the Read cycle 7, 8
L H H L X X Burst Termination Terminate the Burst  
L H H H X X No Operation Continue the Burst  
H X X X X X Device Deselect Continue the Burst  
Read with Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge ILLEGAL 3
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write ILLEGAL  
L H L H BS Column Read ILLEGAL  
L H H L X X Burst Termination ILLEGAL  
L H H H X X No Operation Continue the Burst  
H X X X X X Device Deselect Continue the Burst  
Write with Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge ILLEGAL 3
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write ILLEGAL  
L H L H BS Column Read ILLEGAL  
L H H L X X Burst Termination ILLEGAL  
L H H H X X No Operation Continue the Burst  
H X X X X X Device Deselect Continue the Burst  
Precharging L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge No Operation; Bank(s) idle after tRP  
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write ILLEGAL 3
L H L H BS Column Read ILLEGAL 3
L H H L X X Burst Termination No Operation; Bank(s) idle after tRP  
L H H H X X No Operation No Operation; Bank(s) idle after tRP  
H X X X X X Device Deselect No Operation; Bank(s) idle after tRP  
Row Activating L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge ILLEGAL 3
L L H H BS Row Address Bank Activate ILLEGAL 3, 9
L H L L BS Column Write ILLEGAL 3
L H L H BS Column Read ILLEGAL 3
L H H L X X Burst Termination No Operation; Row Active after tRCD  
L H H H X X No Operation No Operation; Row Active after tRCD  
H X X X X X Device Deselect No Operation; Row Active after tRCD  
Write
Recovering
L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge ILLEGAL 3
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write Start Write; Determine if Auto Precharge 8
L H L H BS Column Read Start Read; Determine if Auto Precharge 8
L H H L X X Burst Termination No Operation; Row Active after tDPL  
L H H H X X No Operation No Operation; Row Active after tDPL  
H X X X X X Device Deselect No Operation; Row Active after tDPL  
Write
Recovering with Auto
Precharge
L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge ILLEGAL 3
L L H H BS Row Address Bank Activate ILLEGAL 3
L H L L BS Column Write ILLEGAL 3, 8
L H L H BS Column Read ILLEGAL 3, 8
L H H L X X Burst Termination No Operation; Precharge after tDPL  
L H H H X X No Operation No Operation; Precharge after tDPL  
H X X X X X Device Deselect No Operation; Precharge after tDPL  
Refreshing L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge ILLEGAL  
L L H H BS Row Address Bank Activate ILLEGAL  
L H L L BS Column Write ILLEGAL  
L H L H BS Column Read ILLEGAL  
L H H L X X Burst Termination No Operation; Idle after tRC  
L H H H X X No Operation No Operation; Idle after tRC  
H X X X X X Device Deselect No Operation; Idle after tRC  
Mode Register Accessing L L L L OP Code Mode Register Set ILLEGAL  
L L L H X X Auto or Self Refresh ILLEGAL  
L L H L BS X Precharge ILLEGAL  
L L H H BS Row Address Bank Activate ILLEGAL  
L H L L BS Column Write ILLEGAL  
L H L H BS Column Read ILLEGAL  
L H H L X X Burst Termination ILLEGAL  
L H H H X X No Operation No Operation; Idle after two clock cycles  
H X X X X X Device Deselect No Operation; Idle after two clock cycles  
  1. All Banks must be idle; otherwise, it is an illegal action.
  2. If CKE0 is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE0 is inactive (low) than the Self Refresh mode is entered.
  3. The Current State refers to only one of the banks. If BAO, 1 selects this bank then the action is illegal. If BAO, 1 selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank.
  4. If CKE0 is inactive (low) than the Power Down mode is entered, otherwise there is a NOP.
  5. The minimum and maximum Active time (tRAS) must be satisfied.
  6. The RAS to CAS Delay (tRCD) must occur before the command is given.
  7. Column address A10/AP is used to determine if the Auto Precharge function is activated.
  8. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
  9. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.