The PC-100 standard

100 MHz clock places higher demands on SDRAMs


The standard
Ever since Intel introduced its 486-class CPUs, the gulf between processor power and the data rate of main memory has widened continuously. And although the latest Intel processors operate at an internal frequency of up to 450 MHz, the clock rate of memories has remained stationary at 66 MHz.

Two-stage caches have been used for many years to boost the performance of PC memory subsystems. The level-one cache is integrated into the silicon of the processor chip, whereas the level-two cache consists of fast SRAMs that are soldered onto the motherboard, integrated into the processor housing, or soldered onto the board of the Slot-1 CPU. This scheme of using two cache levels greatly increases the performance of the memory subsystem when the processor reads and writes data from or to the memory system.

PC 66 versus PC 100

The differences in requirements on memory modules operated at clock rates of 66 MHz and 100 MHz.

  PC 66 / 66 MHz PC 100 / 100 MHz
Row-address-to-column-address delay 2 (preferred) or 3 cycles 2 (preferred) or 3 cycles
CAS latency 2 (preferred) or 3 cycles 2 (preferred) or 3 cycles
Precharge 2 (preferred) or 3 cycles 2 (preferred) or 3 cycles
Signal setup 3 ns 2 ns

Time before CLK

Signal hold-time after CLK 1.5 ns 1 ns
Tac clock-to-data delay 9 ns 6 ns
Toh data hold time after CLK 3 ns 3 ns

The AGP port bypasses the PCI bus.
In addition to the processor, however, other PC components also access
main memory without having a cache at their disposal to speed up their performance. This applies above all to the PCI bus and its peripherals, and to SCSI, IDE, ISA and USB. The addition of the AGP port to motherboards, which bypasses the “slow” PCI bus and is designed to accelerate 3D graphics, now means that the data rates of main
memory need to be increased significantly.Today’s typical main memory comprising SDRAM components attains a maximum data rate of 533 Mbyte/s in burst mode across a 64-bit wide bus at a clock rate of 66 MHz. How-ever, Intel has specified a data rate of 1.6 Gbyte/s per second as the target that the DRAM industry must meet in the near future.
This will not be attained in a single step: Intel is initially increasing the frequency from 66 MHz frequency to 100 MHz. This 100 MHz memory technology is generally called PC100. SDRAMs will continue to be used as the memory components, but the demands on them in terms of their electrical parameters will increase dramatically.
The transition from EDO DRAMs to SDRAMs operating at 66 MHz proved to be no walkover for the PC industry. With FPM and EDO memory, manufacturers standardized specifications over a number of years so that components from different suppliers operated smoothly in all applications; this was not the case with the introduction of the SDRAMs. One reason was that SDRAM components have to be initialized in a special mode to program such parameters as CAS latency and burst length before read and write access is possible. BIOS manufacturers in particular ran into problems on this score. When SDRAMs were introduced as main memories, their power-on and initialization routines, the driver capability of the data out-puts and various other electrical parameters proved to differ so widely from system to system that components from a given manufacturer would operate fine on some motherboards but not at all on others. Although
the international standards committee JEDEC had laid down a framework of conditions, it had failed to define all the parameters in detail.

The move to 100 MHz means tougher specifications.
When the step up from a clock rate of 66 to 100 MHz takes place – corresponding approximately to the frequency of UHF radio – the RF properties of the memory components and the memory-module and motherboard layouts become an issue. Because end-users should continue to have the option of upgrading their PCs with memory modules, aspects such as the characteristics of the SDRAM modules at minimum and maximum memory extensions and thus different capacitive loads must be taken into account in the design. To facilitate the introduction of PC100, Intel has now published specifications for PC SDRAMs and for the layout of memory modules. These specifications may be downloaded from Intel’s web site. A particularly important feature in this context is the tac parameter, also known as the access time from clock or the clock-to-data delay time. This has now been reduced from 9 ns to 6 ns. As the table shows, different latencies are permitted for individual parameters. Whereas it used to be possible to set the access parameters manually in the PC’s BIOS setup routine, this is now done automatically in all more recent computers. For this purpose, an additional 256-byte EEPROM whose first 128 bytes contain all module data are soldered onto the respective modules. This data can include details of the memory organization, key electrical parameters, the encoded name of the manufacturer, and a component serial number. When the computer is configured, this information is read out from the EEPROM of every single DIMM and the memory controller register is set accordingly. If these EEPROMs are incorrectly programmed or not programmed at all, or if an attempt is made to run modules that are designed for 66 MHz operation at 100 MHz, the computer simply will not operate. There are also minor differences in the wiring of the modules between the Intel PC66 specification and the PC SDRAM specification for PC100 – especially regarding assignment to the external clock signals – so that some organization forms of PC100 modules may not run on certain motherboards. It is highly probable that additional BIOS updates will then be required to iron out these differences.

Minor performance gains, initially
If the differences in system performance between 66 MHz and 100 MHz operation with otherwise identical systems are compared – i.e. with the same 333 MHz Pentium II processor – using a benchmark utility such as WINBENCH 98, the initial results are disappointing. The program executes just 2.7% faster. And the PC100 memory bus will
currently make no noticeable difference to PC users working with office programs.
It’s also easy to see why. Pentium II processors with a level-2 cache operating at half the CPU clock are already effectively decoupled from the main memory, i.e. the processor mostly moves data into and out of cache memory and seldom needs to access main memory directly. Matters are different when the AGP bus is also operated in 4x mode instead of today’s 1x or 2x mode. Users of graphics-intensive applications or 3-D games can then really appreciate the advantages of the PC100 bus. New application software also makes effective use of the benefits of this technology.
Depending on the values programmed in the EEPROM, the memory system has different wait times and thus different bandwidths. The difference between mainmemory data transfer rates for the fastest (type 2-2-3) and the slowest (type 3-3-3) modules is roughly 10%. Because users cannot, as a rule, read out the contents of the EEPROMs, each PC100 module has the values of the relevant parameters inscribed on it. Users then know whether they are getting a faster or slower PC100 module.


Access time from clock

If you want to see the access time on an oscilloscope measured in f.x. a system with a 100 MHz clock rate for the memory bus. The determining factor here is the time from when the system clock’s rising edge reaches 1.4 V until the desired datum appears at the data output and also reaches 1.4 V.


Intel’s latest processors now run at internal frequencies of up to 450 MHz, but the clock rate at which memory components operate has remained stationary at 66 MHz. Although this allows memory transfers at 533 Mbyte/s, performance still falls well short of the Intel’s designated target of 1.6 Gbyte/s.
The first step towards higher transfers rates has been to introduce PC100 modules, which support a clock of 100 MHz.